The present invention relates to a semiconductor device; and, more particularly, to a high voltage generation circuit for use in the semiconductor device.
As well-known in the art, a semiconductor memory device is a semiconductor device that stores a lot of data and reads out the stored data. In order to effectively store and read out a lot of data, the semiconductor memory device generates various internal voltages required for its internal operation by using a power supply voltage and a ground voltage provided from outside. For example, as the internal voltages, there are a core voltage used as a driving voltage in a data storage area in which a lot of data are stored, a driving voltage for peripheral areas used in peripheral areas for outputting the data stored in the data storage area outside or providing data received from the outside thereto, and a high voltage and a low voltage used for effective control of a MOS transistor arranged in the data storage area. Among these voltages, the high voltage generally refers to a voltage having a level higher than that of a power supply voltage by a certain level. This high voltage is mainly provided to a gate of the MOS transistor disposed in the data storage area. On the other hand, the low voltage generally refers to a voltage having a level lower than that of a ground voltage by a certain level. This low voltage is mainly used as a bulk voltage of the MOS transistor in the data storage area.
A conventional high voltage generation circuit generates a high voltage that is twice or thrice as high as a level of a power supply voltage by employing the power supply voltage and a ground voltage. It is a tendency that a level of the power supply voltage is gradually being lowered to reduce the power consumption of a semiconductor memory device. Meanwhile, the level of the high voltage generated by the high voltage generation circuit should be constantly maintained in order to drive the MOS transistor arranged in the data storage area. Therefore, the high voltage generation circuit generates a high voltage that is twice as high as the power supply voltage if it can provide the required level of high voltage by boosting the power supply voltage two times. Alternatively, it generates a high voltage that is thrice as high as the power supply voltage if it can provide the required level of high voltage by boosting the power supply voltage three times.
Accordingly, a plurality of MOS transistors arranged in the high voltage generation circuit should be connected to a node in which a voltage level that is twice or thrice as high as the level of the power supply voltage is provided. Since the MOS transistors disposed in the semiconductor memory device are designed to be smaller with the advancement of technologies of semiconductor integration circuits, it is inevitable that they are further weakened as a voltage level is higher than before. Specifically, since the gate length of MOS transistors is shorter, they are further weakened to a higher voltage. It is very difficult for the smaller MOS transistors of the high voltage generation circuit to operate stably when they receive a high voltage that is twice or thrice as high as the power supply voltage. Moreover, in a serious case, these MOS transistors are destroyed.
An example of solving the above problems is that high voltage generation circuits for generating high voltages that are twice and thrice as high as the level of the power supply voltage respectively are disposed separately. In this case, the MOS transistors arranged in the high voltage generation circuits are designed to be different from each other. However, this enlarges the size of a whole circuit to generate the high voltage, and in turn increases power consumption.